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| 1996 data sheet the m pd78p4916 is one of the m pd784915 subseries in the 78k/iv series microcontrollers which incorporate a high-speed and high-performance 16-bit cpu. the m pd78p4916 replaces mask rom with one-time prom and increases on-chip rom and ram capacity compared to the m pd784915. it is suitable for evaluation at system development and for small quantity production. detailed descriptions of functions are provided in the following user's manuals. be sure to read these documents when designing. m pd784915 subseries users manual C hardware : u10444e 78k/iv series user's manual C instruction : u10905e features high-speed instruction execution using 16-bit cpu core ? minimum instruction execution time: 250 ns (at 8-mhz internal clock) on-chip high capacity memory ? prom : 62 kbytes note ? ram : 2048 bytes note note it is possible to change the capacity of the internal prom and the internal ram by specifying the internal memory capacity select (ims) register. ordering information part number package m pd78p4916gf-3ba 100-pin plastic qfp (14 20 mm) document no. u11045ej1v0ds00 (1st edition) date published april 1996 p printed in japan 16-bit single-chip microcontroller the information in this document is subject to change without notice. the mark * shows major revised points. mos integrated circuit m pd78p4916
2 m pd78p4916 78k/iv series products 78k/iv series high-performance 16-bit cpu core high-speed operation on-chip analog circuit for vcr pd78148 subseries m pd78138 subseries m enhanced peripheral hardware 78k/i series pd784915 subseries m pd784915 subseries m m pd78p4916 3 function list (1/2) item function internal prom capacity 62 kbytes note internal ram capacity 2048 bytes note operation clock 16 mhz (internal clock: 8 mhz) low frequency oscillation mode: 8 mhz (internal clock: 8 mhz) low power consumption mode: 32.768 khz (subsystem clock) minimum instruction execution time 250 ns (at 8-mhz internal clock) i/o ports total: 54 input: 8 i/o: 46 real-time output port 11 (including 3 outputs each for pseudo-v sync , head amplifier switch, and chromi- nance rotate) super timer/counter timer/counter compare register capture register remark timer tm0 (16-bit) 3 C unit tm1 (16-bit) 3 1 frc (22-bit) C 6 tm3 (16-bit) 2 1 udc (5-bit) 1 C ec (8-bit) 4 C generates hsw signal edv (8-bit) 1 C divides cfg signal capture register input signal number of bits measurement cycle operation edge cfg 22 125 ns to 524 ms - dfg 22 125 ns to 524 ms - hsw 16 1 m s to 65.5 ms - v sync 22 125 ns to 524 ms - ctl 16 1 m s to 65.5 ms - t reel 22 125 ns to 524 ms - s reel 22 125 ns to 524 ms - special circuit for vcr ? v sync separator, h sync separator ? viss detector, wide-aspect detector ? field identifier ? head amplifier switch/chrominance rotate output circuit general purpose timer timer compare register capture register tm2 (16-bit) 1 C tm4 (16-bit) 1 (capture/compare) 1 tm5 (16-bit) 1 C pwm output ? 16-bit precision: 3 channels (carrier frequency: 62.5 khz) ? 8-bit precision: 3 channels (carrier frequency: 62.5 khz) serial interface 3-wire serial i/o: 2 channels ? busy/strb control available (only 1 channel) a/d converter 8-bit resolution 12 channels, conversion time: 10 m s note it is possible to change the capacity of the internal prom and the internal ram by specifying the internal memory capacity select (ims) register. 4 m pd78p4916 function list (2/2) item function analog unit ? ctl amplifier ? recctl driver (supports re-write operation) ? dfg amplifier, dpg comparator, cfg amplifier ? dpfg separator (three-value) ? reel fg comparator (2 channels) ? csync comparator interrupt programmable 4 levels, vectored interrupt, macro service, context switching external 9 (including nmi) internal 19 (including software interrupt) standby function halt mode/stop mode low-power consumption mode: halt mode release from stop mode by nmi pins active edge, watch interrupt (intw), or intp1/intp2/key0-key4 pins input. watch function 0.5-sec interval, capable of low-voltage operation (v dd = 2.7 v) power supply voltage v dd = 2.7 to 5.5 v package 100-pin plastic qfp (14 20 mm) * * m pd78p4916 5 pin configuration (top view) (1) normal operation mode 100-pin plastic qfp (14 20 mm) m pd78p4916gf-3ba caution connect the ic (internally connected) pin to v ss directly. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p64 p65/hwin p66/pwm4 p67/pwm5 p60/strb/clo p61/sck1/buz p62/so1 p63/si1 pwm0 pwm1 sck2 so2 si2/busy v dd xt1 xt2 v ss x2 x1 reset ic pto02 pto01 pto00 p87/pto11 p86/pto10 p85/pwm3 p84/pwm2 p83/rotc p82/hasw ani9 ani8 p77/ani7 p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 av ref av dd2 p96 p95/key4 p94/key3 p93/key2 p92/key1 p91/key0 p90/env nmi intp0 intp1 p00 p01 p02 p03 p04 p05 p06 csyncin reel0in/intp3 reel1in dfgin dpgin cfgcpin cfgampo cfgin av dd1 av ss1 vrefc ctlout2 ctlout1 ctlin recttl recttl+ ctldly av ss2 ani11 ani10 p80 p57 p56 p55 p54 p53 p52 p51 p50 v ss v dd p47 p46 p45 p44 p43 p42 p41 p40 p07 intp2 6 m pd78p4916 ani0-ani11 : analog input p00-p07 : port0 av dd1 , av dd2 : analog power supply p40-p47 : port4 av ss1 , av ss2 : analog ground p50-p57 : port5 av ref : analog reference voltage p60-p67 : port6 busy : serial busy p70-p77 : port7 buz : buzzer output p80, p82-p87 : port8 cfgampo : capstan fg amplifier output p90-p96 : port9 cfgcpin : capstan fg capacitor input pto00-pto02, : programmable timer output cfgin : analog unit input pto10, pto11 clo : clock output pwm0 - pwm5 : pulse width modulation output csyncin : analog unit input recctl+, recctlC : recctl output/pbclt input ctldly : control delay input reel0in, reel1in : analog unit input ctlin : ctl amplifier input capacitor reset : reset ctlout1, ctlout2 : ctl amplifier output rotc : chrominance rotate output dfgin : analog unit input sck1, sck2 : serial clock dpgin : analog unit input si1, si2 : serial input env : envelope input so1, so2 : serial output hasw : head amplifier switch output strb : serial strobe hwin : hardware timer external input v dd : power supply ic : internally connected vrefc : reference amplifier capacitor intp0-intp3 : interrupt from peripherals vss : ground key0-key4 : key return x1, x2 : crystal (main system clock) nmi : nonmaskable interrupt xt1, xt2 : crystal (subsystem clock) m pd78p4916 7 cautions (l) : connect to v ss via pull-down resistors individually. v ss : connect to ground. open : leave this pin unconnected. reset : apply low level. a0 - a16 : address bus reset : reset d0 - d7 : data bus v dd : power supply ce : chip enable v pp : programming power supply oe : output enable v ss : ground pgm : program (2) prom programming mode ? 100-pin plastic qfp (14 20 mm) m pd78p4916gf-3ba 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 3536 37 38 39 4041 42 43 44 4546 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 69 100 99 98 97 9695 94 93 92 9190 89 88 87 8685 84 83 82 81 oe ce pgm (l) open (l) v dd v ss open v ss open v ss reset ic/v pp open (l) ? ? y ? ? t ? ? y ? ? t y t y t y t ? y ? t (l) open (l) v dd v ss open open (l) (l) (l) open v ss y t y t y t (l) (l) v dd y t a9 (l) d0 d1 d2 d3 d4 d5 d6 ? ? ? y ? ? ? t ? ? ? ? ? y ? ? ? ? ? t (l) a15 a14 a13 a12 a11 a10 a16 a8 v ss v dd a7 a6 a5 a4 a3 a2 a1 a0 d7 8 m pd78p4916 internal block diagram nmi rom 62 kbytes d0 - d7 reset xt1 x2 x1 v dd v ss oe pgm v pp intp0 - intp3 pwm0 - pwm5 pto00 - pto02 pto10, pto11 vrefc reel0in reel1in csyncin dfgin dpgin cfgin cfgampo cfgcpin ctlout1 ctlout2 ctlin recctl+ recctl ctldly av dd1 , av dd2 av ss1 , av ss2 av ref ani0 - ani11 si1 so1 sck1 si2/busy so2 sck2 strb serial interface 2 serial interface 1 analog unit & a/d converter super timer unit interrupt control system control clock output buzzer output key input real-time output port port4 port0 port5 port6 port7 port8 port9 xt2 a0 - a16 ce clo buz key0 - key4 p00 - p07 p80, p82, p83 p40 - p47 p00 - p07 p50 - p57 p60 - p67 p70 - p77 p80, p82 - p87 p90 - p96 78k/iv 16-bit cpu core (ram 512 bytes) ram 1536 bytes used in prom programming mode m pd78p4916 9 system configuration example camcorder pseudo-vertical sync signal dfg dpg cfg dfgin dpgin pwm0 cfgin pwm1 port csyncin pto00 pto01 p80 x1 x2 xt1 xt2 port strb port busy so2 sck2 port intp0 so1 si1 sck1 port intp0 sck so si port cs clk data busy lcd c/d cs clk data busy stb osd pd6456 pd7225 pd78356 port port pd78p4916 m m m m m 16 mhz 32.768 khz drum motor driver driver capstan motor audio-video signal processor key matrix microcontroller for camera control camera block lcd display panel mechanical block m recctl+ ctl head recctl pwm2 m driver loading motor intp2 pc2800a m remote control receive signal signals from remote controller composite sync signal video head switch audio head switch 10 m pd78p4916 deck-type vcr key matrix mechanical block tuner unit dfg dpg cfg dfgin dpgin pwm0 cfgin pwm1 recctl+ recctl pwm2 pwm4 p80 reel1in x1 x2 xt1 xt2 port port so1 si1 port pd78p4916 m m m 8 mhz 32.768 khz drum motor driver driver driver capstan motor ctl head loading motor m driver reel motors m driver reel0in pwm3 pwm5 pto01 pto00 csyncin port low-frequency oscillation mode m reel fg1 reel fg0 pc2800a m signals from remote controller remote control receive signal intp2 stb clk dout pd16311 m fip c/d fip din so2 sck2 port cs clk data osd pd6454 m audio-video signal processor unit composite synchronous signal video head switch audio head switch pseudo-vertical synchronous signal sck1 tm m pd78p4916 11 contents 1. differences between m pd78p4916 and m pd784915, m pd784916a 12 2. pin function 13 2.1 normal operation mode 13 2.2 prom programming mode (v pp 3 5 v, reset = l) 15 2.3 pin i/o circuits and recommended connection of unused pins 16 3. internal memory capacity select register (ims) 20 4. prom programming 21 4.1 operation mode 21 4.2 prom write procedure 23 4.3 prom read procedure 27 4.4 screening one-time prom versions 27 5. electrical specifications 28 6. package drawing 46 7. recommended soldering conditions 47 appendix a. development tools 4 8 appendix b. socket drawing and recommended footprint 50 appendix c. related documents 52 * * * * 12 m pd78p4916 1. differences between m pd78p4916 and m pd784915, m pd784916a other than the memory types, their capacities, and memory-related points, the functions of the three devices are identical: the m pd78p4916 incorporates a one-time prom that is rewritable by users, while the m pd784915 and 784916a contain mask roms. table 1-1 shows the differences among these devices. be sure to keep in mind these differences especially when debugging and pre-producing the application system with the prom version and then mass-producing it with the mask-rom version. for the details about the cpu functions and on-chip hardware, refer to the m pd784915 subseries users manualhardware (u10444e). table 1-1. differences among m pd784915 subseries devices parameters m pd78p4916 m pd784915 m pd784916a internal rom one-time prom mask rom mask rom 62 kbytes note 48 kbytes 62 kbytes internal ram 2048 bytes note 1280 bytes 1280 bytes internal memory size select register (ims) provided not provided not provided pinouts pins related to prom writing and reading are provided on the m pd78p4916. other there are differences in noise immunity, noise radiation, and some electrical specifications, because of the differences in circuit complexity and mask layout. note the internal prom and ram capacities of the m pd78p4916 can be changed through its internal memory size select register (ims). caution there are differences in noise immunity and noise radiation between the prom and mask-rom versions. when pre-producing the application set with the prom version and then mass- producing it with the mask-rom version, be sure to conduct sufficient evaluations for the set using consumer samples (not engineering samples) of the mask-rom version. * m pd78p4916 13 2. pin function 2.1 normal operation mode (1) port pins pin name input/output alternate function description p00 - p07 i/o real-time 8-bit input/output port (port0) output port ? specifiable to input or output mode bitwise. ? with software-specifiable on-chip pull-up resistors (p00 - p07). p40 - p47 i/o C 8-bit input/output port (port4) ? specifiable to input or output mode bitwise. ? with software-specifiable on-chip pull-up resistors (p40 - p47). p50 - p57 i/o C 8-bit input/output port (port5) ? specifiable to input or output mode bitwise. ? with software-specifiable on-chip pull-up resistors (p50 - p57). p60 i/o strb/clo 8-bit input/output port (port6) p61 sck1/buz ? specifiable to input or output mode bitwise. p62 so1 ? with software-specifiable on-chip pull-up resistors p63 si1 (p60 - p67). p64 C p65 hwin p66 pwm4 p67 pwm5 p70 - p77 input ani0 - ani7 8-bit input port (port7) p80 i/o real-time for pseudo-v sync output 7-bit input/output port (port8) p82 output port for hasw output ? specifiable to input or output p83 for rotc output mode bitwise. p84 pwm2 ? with software-specifiable on-chip p85 pwm3 pull-up resistors (p80, p82 - p87) p86 pto10 p87 pto11 p90 i/o env 7-bit input/output port (port9) p91 - p95 key0 - key4 ? specifiable to input or output mode bitwise. p96 C ? with software-specifiable on-chip pull-up resistors (p90 - p96). 14 m pd78p4916 (2) non-port pins (1/2) pin name input/output alternate function description reel0in input intp3 reel fg inputs reel1in C dfgin C drum fg, pfg input (three-value) dpgin C drum pg input cfgin C capstan fg input csyncin C composite sync input cfgcpin C cfg comparator input cfgampo output C cfg amplifier output pto00 output C programmable timer outputs of super timer unit pto01 C pto02 C pto10 p86 pto11 p87 pwm0 output C pwm outputs of super timer unit pwm1 C pwm2 p84 pwm3 p85 pwm4 p66 pwm5 p67 hasw output p82 head amplifier switch output rotc output p83 chrominance rotate output env input p90 envelope input si1 input p63 serial data input (serial interface channel 1) so1 output p62 serial data output (serial interface channel 1) sck1 i/o p61/buz serial clock input/output (serial interface channel 1) si2 input busy serial data input (serial interface channel 2) so2 output C serial data output (serial interface channel 2) sck2 i/o C serial clock input/output (serial interface channel 2) busy input si2 serial busy input (serial interface channel 2) strb output p60/clo serial strobe output (serial interface channel 2) ani0 - ani7 analog inputs p70 - p77 analog inputs for a/d converter ani8 - ani11 C ctlin C C ctl amplifier input capacitor ctlout1 output C ctl amplifier output ctlout2 i/o C logic input/ctl amplifier output recctl+, recctlC i/o C recctl output/pbctl input ctldly C C external time-constant connection (to rewrite recctl) vrefc C C ac ground for vref amplifier nmi input C non-maskable interrupt request input m pd78p4916 15 (2) non-port pins (2/2) pin name input/output alternate function description intp0 - intp2 input C external interrupt request input intp3 input reel0in key0 - key4 input p91 - p95 key input signal clo output p60/strb clock output buz output p61/sck1 buzzer output hwin input p65 hardware timer external input reset input C reset input x1 input C crystal resonator connection for main system clock oscillation x2 C xt1 input C crystal resonator connection for subsystem clock oscillation xt2 C crystal resonator connection for clock oscillation of watch av dd1 , av dd2 C C positive power supply for analog unit av ss1 , av ss2 C C gnd for analog unit av ref C C reference voltage input to a/d converter v dd C C positive power supply to digital unit v ss C C gnd of digital unit ic C C internally connected. connect directly to v ss . 2.2 prom programming mode (v pp 3 5 v, reset = l) pin name input/output function v pp C set prom programming mode high voltage applied at program write/verify operation reset input low level input for setting prom programming mode a0 - a16 address input d0 - d7 i/o data input/output pgm input program inhibit input in prom programming mode ce prom enable input / programming pulse input oe read strobe input to prom v dd C positive power supply v ss gnd potential 16 m pd78p4916 2.3 pin i/o circuits and recommended connection of unused pins table 2-1 shows the input/output circuit types of the devices pins and the recommended connection of the pins which are unnecessary to the users application. the circuit diagrams for the i/o circuits are shown in figure 2-1. table 2-1. pin i/o circuits and recommended connection of unused pins (1/2) pins i/o circuit types direction recommended connection of unused pins p00-p07 5-a i/o input mode: connect to v dd . p40-p47 output mode: leave unconnected. p50-p57 p60/strb/clo p61/sck1/buz 8-a p62/so1 5-a p63/si1 8-a p64 5-a p65/hwin 8-a p66/pwm4 5-a p67/pwm5 p70/ani0-p77/ani7 9 input connect to v ss . p80 5-a i/o input mode: connect to v dd . p82/hasw output mode: leave unconnected. p83/rotc p84/pwm2 p85/pwm3 p86/pto10 p87/pto11 p90/env p91/key0-p95/key4 8-a p96 5-a si2/busy 2-a input connect to v dd . so2 4 output high-impedance mode: connect to v ss via a pull-down resistor. otherwise: leave unconnected. sck2 8-a i/o input mode: connect to v dd . output mode: leave unconnected. ani8-ani11 7 input connect to v ss . recctl+, recctlC i/o when enctl = 0 and enrec = 0: connect to v ss . remark enctl: bit 1 of the amplifier control register (ampc) enrec: bit 7 of the amplifier mode register 0 (ampm0) * m pd78p4916 17 table 2-1. pin i/o circuits and recommended connection of unused pins (2/2) pins i/o circuit types direction recommended connection of unused pins dfgin input endrum = 0: connect to v ss . dpgin endrum = 0, or endrum = 1 and selpgsepa = 0: connect to v ss . cfgin, cfgcpin encap = 0: connect to v ss . csyncin encsyn = 0: connect to v ss . reel0in/intp3, reel1in enreel = 0: connect to v ss . ctlout1 output leave unconnected. ctlout2 i/o when enctl and encomp = 0 and 0: connect to v ss . enctl = 1: leave unconnected. cfgampo output leave unconnected. ctlin when enctl = 0: leave unconnected. vrefc when enctl, encap, and encomp = 0, 0, and 0: leave unconnected. ctldly leave unconnected. pwm0, pwm1 3 output leave unconnected. pto00-pto02 nmi 2 input connect to v dd . intp0 connect to v dd or v ss . intp1, intp2 2-a input connect to v dd . av dd1 , av dd2 connect to v dd . av ref , av ss1 , av ss2 connect to v ss . reset 2 xt1 connect to v ss . xt2 leave unconnected. ic connect directly to v ss . remark endrum: bit 2 of the amplifier control register (ampc) selpgsepa: bit 2 of the amplifier mode register 0 (ampm0) encap: bit 3 of the amplifier control register (ampc) encsyn: bit 5 of the amplifier control register (ampc) enreel: bit 6 of the amplifier control register (ampc) enctl: bit 1 of the amplifier control register (ampc) encomp: bit 4 of the amplifier control register (ampc) 18 m pd78p4916 figure 2-1. pin i/o circuit diagrams (1/2) in schmitt triggered input with hysteresis characteristics. in v dd p-ch pullup enable data p-ch n-ch out v dd v dd p-ch n-ch out data output disable push-pull output that can also set the output to the high-impedance state (both p-ch and n-ch transistors are turned off.) v dd p-ch n-ch p-ch v dd in/ out pullup enable data output disable p-ch n-ch v ref (threshold voltage) in comparator v dd p-ch n-ch in/ out data output disable v dd p-ch pullup enable input enable type 2 type 2-a type 3 type 4 type 8-a type 7 type 5-a schmitt triggered input with hysteresis characteristics. m pd78p4916 19 figure 2-1. pin i/o circuit diagrams (2/2) comparator v ref (threshold voltage) n-ch p-ch in input enable type 9 20 m pd78p4916 3. internal memory capacity select register (ims) internal memory capacity select register (ims) specifies the effective area of on-chip memory (prom, ram) of the m pd78p4916. setting this register is required when the capacity of the rom or ram in the mask version is smaller than that of the m pd78p4916. if the memory capacity of the m pd78p4916 is appropriately defined using this register, bugs in application programs due to accessing an address beyond the memory capacity of the actual chip can be avoided. the ims register is write-only register. to write this register, use the 8-bit manipulation instruction. the register is initialized to ffh by reset input (rom: 62 kbytes, ram: 2048 bytes). figure 3-1. internal memory capacity select register (ims) format caution the m pd78p4916 has the ims and the m pd784915 and 784916a do not have it. however, if a write instruction to ims is executed in the m pd784915 or 784916a, it does not cause conflicts or malfunctions. 7654 2 310 11 1 rom1 rom0 1 ram1 ram0 ims fffch ffh w r/w state at reset address ram1 ram0 0 1 1 1 specification of internal ram capacity 1280 bytes 2048 bytes setting prohibited rom1 rom0 1 1 0 1 specification of internal rom capacity 48 kbytes 62 kbytes other setting prohibited other * m pd78p4916 21 4. prom programming the m pd78p4916 has on-chip 62-kbyte prom as the program memory. the prom programming mode is entered by setting v dd , ic/v pp , and reset pins as specified. for the settings of the unused pins in this mode, refer to the drawing of (2) prom programming mode in the section pin configuration (top view). 4.1 operation mode the prom programming mode is entered by applying +5 v or +12 v to the ic/v pp pin, +5 v or +6.5 v to the v dd pins, and low-level voltage to the reset pin. table 4-1 shows the operation mode specified by the ce, oe, and pgm pins. it is possible to read the contents of prom by setting up read operation mode. table 4-1. operation mode of prom programming pins reset ic/v pp v dd ce oe pgm d0 - d7 operation mode page data latch l +12.5 v +6.5 v h l h data input page write h h l high impedance byte write l h l data input program verify l l h data output program inhibit h h high impedance ll read +5 v +5 v l l h data output output disable l h high impedance standby h high impedance remark : low or high level 22 m pd78p4916 (1) read mode by setting ce = l and oe = l, the device enters the read mode. (2) output disable mode by setting oe = h, the device enters the output disable mode, where data output pins go to high impedance state. therefore it is possible to read data from a specified device by enabling only the oe pin of the device to be read, if two or more m pd78p4916s are connected to a data bus. (3) standby mode by setting ce = h, the device enters the standby mode. in this mode, data output pins go to high impedance state regardless of the oe pin condition. (4) page data latch mode by setting ce = h, pgm = h, and oe = l at the beginning of page programming mode, the device enters the page data latch mode. in this mode, 4-byte data are latched in page units (consisting of 4 bytes) to internal address/data latch circuit. (5) page programming mode after one-page data (consisting of 4 bytes) and their address are latched in the page data latch mode, the page programming operation is executed by applying 0.1-ms programming pulse (active low) to the pgm pin under ce = h, oe = h conditions. following that operation, the programming data is verified by setting ce = l and oe = l. when data is not programmed by one programming pulse, the write and verify operations are repeated x times (x 10). (6) byte programming mode applying 0.1-ms programming pulse (active low) to the pgm pin under ce = l and oe = h condition, byte programming operation is executed. next, the programming data is verified by setting oe = l. when data is not programmed by one programming pulse, the write and verify operations are repeated x times (x 10). (7) program verify mode by setting ce = l, pgm = h, and oe = l, the device enters the program verify mode. check whether data is programmed correctly or not in this mode after write operation. (8) program inhibit mode when the oe pins, v pp pins, and d0-d7 pins of two or more m pd78p4916s are connected in parallel, use program inhibit mode to write data to one of those devices. programming is executed in the page programming mode or byte programming mode as mentioned above. at that time, data is not programmed to a device for which high level voltage is applied to the pgm pin. m pd78p4916 23 4.2 prom write procedure figure 4-1. flowchart in page programming mode remarks 1. g = start address 2. n = end address of the program start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 latch address = address + 1 latch address = address + 1 latch address = address + 1 latch x = x+1 0.1-ms programming pulse verify 4 bytes pass fail address = n ? yes v dd = 4.5 to 5.5 v, v pp = v dd fail pass no all pass verify all bytes write operation end defective x = 10? yes no address = address + 1 24 m pd78p4916 figure 4-2. operation timing in page programming mode page data latch page programming program verify address input address input hi-z data input data output hi-z hi-z d0 - d7 a0, a1 a2 - a16 v pp v pp v dd v dd +1.5 v dd v dd v ih ce v il v ih v il v ih v il pgm oe m pd78p4916 25 figure 4-3. flowchart in byte programming mode remarks 1. g = start address 2. n = end address of the program v dd = 6.5 v, v pp = 12.5 v address = g x = 0 x = x+1 0.1-ms programming pulse verify pass fail address = n ? yes v dd = 4.5 to 5.5 v, v pp = v dd fail pass no all pass verify all bytes write operation end defective x = 10? yes no address = address + 1 start 26 m pd78p4916 programming program verify address input hi-z data input data output hi-z hi-z d0 - d7 a0 - a16 v pp v pp v dd v dd +1.5 v dd v dd v ih ce v il v ih v il v ih v il pgm oe figure 4-4. operation timing in byte programming mode cautions 1. apply voltage to v dd before applying voltage to v pp , and cut off v dd voltage after v pp voltage is cut off. 2. the voltage including overshoot applied to v pp pin must be kept less than +13.5 v. 3. if a device is inserted or removed while +12.5 v is applied to v pp pin, it may be adversely affected in reliability. m pd78p4916 27 4.3 prom read procedure the contents of prom can be read onto external data bus (d0-d7) as described below: (1) fix reset pin to low and supply +5 v to v pp pin. connect other unused pins as specified in (2) prom programming mode in section pin configuration (top view)." (2) supply +5 v to the v dd and v pp pins. (3) input the address of the data to be read to the a0-a16 pins. (4) enter the read mode (ce = l, oe = l). (5) output data to d0-d7 pins. the above operation timing from (2) to (5) is shown in figure 4-5. figure 4-5. prom read timing 4.4 screening one-time prom versions the one-time prom version ( m pd78p4916gf-3ba) cannot be completely tested by nec for shipment because of its structure. for screening, it is recommended to verify prom after storing the necessary data under the following conditions: storage temperature storage time 125 ?c 24 hours address input hi-z data output hi-z d0 - d7 a0 - a16 oe (input) ce (input) 28 m pd78p4916 5. electrical specifications absolute maximum ratings (t a = 25 ?c) parameter symbol conditions ratings unit supply voltage v dd v dd C av dd1 0.5 v C0.5 to +7.0 v av dd1 v dd C av dd2 0.5 v C0.5 to +7.0 v av dd2 av dd1 C av dd2 0.5 v C0.5 to +7.0 v av ss1 C0.5 to +0.5 v av ss2 C0.5 to +0.5 v input voltage v i C0.5 to v dd +0.5 v analog input voltage v ian v dd 3 av dd2 C0.5 to av dd2 +0.5 v (ani0-ani11) v dd < av dd2 C0.5 to v dd +0.5 v output voltage v o C0.5 to v dd +0.5 v output current, low i ol per pin 15 ma total of all output pins 100 ma output current, high i oh per pin C10 ma total of all output pins C50 ma operating ambient t a C10 to +70 ?c temperature storage temperature t stg C65 to +150 ?c caution if any of the above paramet ers exceeds the absolute maximum ratings, even momentarily, device reliability may be impaired. the absolute maximum ratings are values that may physically damage the product. be sure to use the product within the ratings. operating conditions clock frequency operating ambient operating condition supply voltage (v dd ) temperature (t a ) 4 mhz f xx 16 mhz C10 to +70 ?c all functions +4.5 to +5.5 v cpu function only +4.0 to +5.5 v 32 khz f xt 35 khz subclock operation (cpu, watch, +2.7 to +5.5 v and port functions only) * m pd78p4916 29 oscillator characteristics (main clock) (t a = e10 to +70 ?c, v dd = av dd = 4.0 to 5.5 v, v ss = av ss = 0 v) resonator recommended circuit item min. max. unit crystal resonator oscillation frequency (f xx ) 4 16 mhz oscillator characteristics (subclock) (t a = C10 to +70 ?c, v dd = av dd = 2.7 to 5.5 v, v ss = av ss = 0 v) resonator recommended circuit item min. max. unit crystal resonator oscillation frequency (f xt ) 32 35 khz caution when using the main system clock and subsystem clock oscillators, wiring in the area enclosed with the dotted lines should be carried out as follows to avoid an adverse effect from wiring capacitance: ? wiring should be as short as possible. ? wiring should not cross other signal lines. wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss . do not ground wiring to a ground pattern in which high current flows. ? do not fetch a signal from the oscillator. as the amplification degree of the subsystem clock oscillator is low to reduce current consumption, pay particular attention to the wiring method. x1 x2 v ss c1 c2 xt1 xt2 v ss c1 c2 30 m pd78p4916 dc characteristics (t a = e10 to +70 ?c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input voltage, low v il1 other than pins indicated in note 1 below 0 0.3v dd v v il2 pins indicated in note 1 below 0 0.2v dd v v il3 x1, x2 0 0.4 v input voltage, high v ih1 other than pins indicated in note 1 below 0.7v dd v dd v v ih2 pins indicated in note 1 below 0.8v dd v dd v v ih3 x1, x2 v dd C0.5 v dd v output voltage, low v ol1 i ol = 5.0 ma (pins listed in note 2 below) 0.6 v v ol2 i ol = 2.0 ma 0.45 v v ol3 i ol = 100 m a 0.25 v output voltage, v oh1 i oh = C1.0 ma v dd C1.0 v high v oh2 i oh = C100 m av dd C0.4 v input leakage current i li 0 v i v dd 10 m a output leakage i lo 0 v o v dd 10 m a current v dd power supply i dd1 operation mode f xx = 16 mhz 35 55 ma current f xx = 8 mhz (low frequency oscillation mode) internal main clock operation at 8 mhz f xt = 32.768 khz 0.9 1.2 ma subclock operation (cpu, watch, port) v dd = 2.7 v i dd2 halt mode f xx = 16 mhz 15 27.5 ma f xx = 8 mhz (low frequency oscillation mode) internal main clock operation at 8 mhz f xt = 32.768 khz 30 60 m a subclock operation (cpu, watch, port) v dd = 2.7 v data retention voltage v dddr stop mode 2.5 v data retention i dddr stop mode subclock oscillation 36 75 m a current note 3 v dddr = 5.0 v stop mode subclock oscillation 3.5 15 m a v dddr = 2.7 v stop mode subclock suspended 1.5 10 m a v dddr = 2.5 v pull-up resistor r l v i = 0 v 25 55 110 k w notes 1. reset, ic, nmi, intp0-intp2, p61/sck1/buz, p63/si1, sck2, si2/busy, p65/hwin, p91/key0-p95/key4. 2. p46, p47 3. when subclock is suspended at stop mode, disconnect feedback resistor and connect xt1 pin to the v dd potential. m pd78p4916 31 ac characteristics cpu and peripheral unit operation clocks (t a = e10 to +70 ?c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions typ. unit cpu operation clock cycle time t clk f xx = 16 mhz v dd = av dd = 4.0 to 5.5 v 125 ns cpu function only f xx = 16 mhz f xx = 8 mhz, low frequency oscillation mode (cc bit7 = 1) peripheral unit operation clock t clk1 f xx = 16 mhz 125 ns cycle time f xx = 8 mhz, low frequency oscillation mode (cc bit7 = 1) serial interface (1) sion: n = 1, 2 (t a = C10 to +70 ?c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. max. unit serial clock cycle time t cysk input external clock 1.0 m s output f clk1 /8 1.0 m s f clk1 /16 2.0 m s f clk1 /32 4.0 m s f clk1 /64 8.0 m s f clk1 /128 16 m s f clk1 /256 32 m s serial clock high/low level width t wskh input external clock 420 ns t wskl output internal clock t cysk /2C50 ns sin set-up time (to sckn - )t sssk 100 ns sin hold time (from sckn - )t hssk 400 ns son output delay time (from sckn ) t dssk 0 300 ns remarks 1. f clk1 : operation clock for peripheral unit (8 mhz) 2. n = 1, 2 (2) only sio2 (t a = C10 to +70 ?c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. max. unit sck2(8) - ? strb - t dstrb t wskh t cysk strobe high level width t wstrb t cysk C30 t cysk +30 ns busy setup time (to busy detection timing) t sbusy 100 ns busy hold time (from busy detection timing) t hbusy 100 ns busy inactive ? sck2(1) t lbusy t cysk +t wskh remarks 1. the value in the parentheses following sck2 indicates the sequential number of the sck2. 2. busy detection timing is (n + 2) t cysk (n = 0, 1,...) after sck2(8) - . 3. busy inactive ? sck2(1) is a value at the time data is already written in sio2. 32 m pd78p4916 other operations (t a = e10 to +70 ?c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. max. unit timer unit input low level width t wctl at dfgin, cfgin, dpgin, reel0in, t clk1 ns reel1in logic level input timer unit input high level width t wcth at dfgin, cfgin, dpgin, reel0in, t clk1 ns reel1in logic level input timer unit input signal valid edge t perin dfgin, cfgin and dpgin input 2 m s input cycle csyncin low level width t wcr1l digital noise eliminator not used 8t clk1 ns digital noise eliminator used 108t clk1 ns (intm2 bit 4 = 0) digital noise eliminator used 180t clk1 ns (intm2 bit 4 = 1) csyncin high level width t wcr1h digital noise eliminator not used 8t clk1 ns digital noise eliminator used 108t clk1 ns (intm2 bit 4 = 0) digital noise eliminator used 180t clk1 ns (intm2 bit 4 = 1) digital noise eliminated pulse t wsep intm2 bit 4 = 0 104t clk1 ns eliminator width intm2 bit 4 = 1 176t clk1 ns passed pulse width intm2 bit 4 = 0 108t clk1 ns intm2 bit 4 = 1 180t clk1 ns nmi low level width t wnil v dd = av dd = 2.7 to 5.5 v 10 m s nmi high level width t wnih v dd = av dd = 2.7 to 5.5 v 10 m s intp0 and intp3 low level width t wipl0 2t clk1 ns intp0 and intp3 high level width t wiph0 2t clk1 ns intp1, key0 - key4 low level t wipl1 other than in stop mode 2t clk1 ns width when cancelling stop mode 10 m s intp1, key0 - key4 high level t wiph1 other than in stop mode 2t clk1 ns width when cancelling stop mode 10 m s intp2 low level width t wipl2 main clock opera tion sampled at f clk 2t clk1 ns in normal mode sampled at f clk /128 32 note m s subclock operation sampled at f clk 61 m s in normal mode sampled at f clk /128 7.9 note ms when cancelling stop mode 10 m s intp2 high level width t wiph2 main clock operation sampled at f clk 2t clk1 ns in normal mode sampled at f clk /128 32 note m s subclock operation sampled at f clk 61 m s in normal mode sampled at f clk /128 7.9 note ms when cancelling stop mode 10 m s reset low level width t wrsl 10 m s note if a high level or low level is input two times in succession during the sampling period, high level or low level is detected. remark t clk1 : operation clock cycle time for peripheral unit (125 ns). m pd78p4916 33 clock output operation (t a = e10 to +70 ?c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol expression min. max. unit clo cycle time t cycl 250 2000 ns clo low level width t cll t cycl /2 50 75 1050 ns clo high level width t clh t cycl /2 50 75 1050 ns clo rising time t clr 50 ns clo falling time t clf 50 ns data retention characteristics (t a = C10 to +70 ?c, v dd = av dd = 2.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input voltage, low v il pins listed in note below 0 0.1v dddr v input voltage, high v ih 0.9v dddr v dddr v note reset, ic, nmi, intp0-intp2, p61/sck1/buz, p63/si1, sck2, si2/busy, p65/hwin, p91/key0-p95/key4 watch function (t a = C10 to +70 ?c, v dd = av dd = 2.7 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. max. unit subclock oscillation retention v ddxt 2.7 v voltage hardware watch function operation v ddw 2.7 v voltage subclock oscillation suspension detection flag (t a = C10 to +70 ?c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. max. unit oscillation suspension detection t oscf 45 m s width a/d converter characteristics (t a = C10 to +70 ?c, v dd = av dd = av ref = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 bit total error av ref = v dd 2.0 % quantization error 1/2 lsb conversion time t conv adm bit 4 = 0 160t clk1 m s adm bit 4 = 1 80t clk1 m s sampling time t samp adm bit 4 = 0 32t clk1 m s adm bit 4 = 1 16t clk1 m s analog input voltage v ian 0av ref v analog input impedance z an 1000 m w av ref current ai ref 0.4 1.2 ma 34 m pd78p4916 vref amplifier (t a = 25 ?c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit reference voltage v ref 2.35 2.50 2.65 v charge current i chg ampm0.0 is set to 1 300 m a for pins listed in note below. note recctl+, recctlC, cfgin, cfgcpin, dfgin, dpgin, csyncin, reel0in, reel1in ctl amplifier (t a = 25 ?c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit ctl+, C input resistance r ictl 2510k w feedback resistance r fctl 20 50 100 k w bias resistance r bctl 20 50 100 k w minimum voltage gain g ctlmin 17 20 22 db maximum voltage gain g ctlmax 71 75 db gain switching step s gain 1.77 db common mode signal rejection cmr dc, voltage gain: 20 db 50 db comparator set voltage for v pbctlhs v ref +0.47 v ref +0.50 v ref +0.53 v waveform regulation, high comparator reset voltage for v pbctlhr v ref +0.27 v ref +0.30 v ref +0.33 v waveform regulation, high comparator set voltage for v pbctlls v ref C0.53 v ref C0.50 v ref C0.47 v waveform regulation, low comparator reset voltage for v pbctllr v ref C0.33 v ref C0.30 v ref C0.27 v waveform regulation, low comparator high voltage for clt flag s v fsh v ref +1.00 v ref +1.05 v ref +1.10 v comparator low voltage for clt flag s v fsl v ref C1.10 v ref C1.05 v ref C1.00 v comparator high voltage for clt flag l v flh v ref +1.40 v ref +1.45 v ref +1.50 v comparator low voltage for clt flag l v fll v ref C1.50 v ref C1.45 v ref C1.40 v m pd78p4916 35 cfg amplifier (ac coupling) (t a = 25 ?c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit voltage gain 1 g cfg1 f i = 2 khz, open loop 50 db voltage gain 2 g cfg2 f i = 2 khz, open loop 34 db cfgampo output current, high i ohcfg dc C1 ma cfgampo output current, low i olcfg dc 0.4 ma comparator high voltage v cfgh v ref +0.09 v ref +0.12 v ref +0.15 v comparator low voltage v cfgl v ref C0.15 v ref C0.12 v ref C0.09 v duty precision p duty see note below. 49.7 50.0 50.3 % note the following circuit and input signal conditions are assumed. ? input signal: sine wave input (5 mv p-p ), f i = 1 khz ? voltage gain: 50 db dfg amplifier (ac coupling) (t a = 25 ?c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit voltage gain g dfg f i = 900 hz, open loop 50 db feedback resistance r fdfg 160 400 640 k w input protect resistance r idfg 150 w comparator high voltage v dfgh v ref +0.07 v ref +0.10 v ref +0.14 v comparator low voltage v dfgl v ref C0.14 v ref C0.10 v ref C0.07 v caution the resistance of the pin to be connected to the dfgin pin must be below 16 k w . if the resistance is higher than the limit, the dfg amplifier may oscillate. dpg comparator (ac coupling) (t a = 25 ?c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input impedance z idpg 20 50 100 k w comparator high voltage v dpgh v ref +0.02 v ref +0.05 v ref +0.08 v comparator low voltage v dpgl v ref C0.08 v ref C0.05 v ref C0.02 v 330 k w cfgin pd78p4916 cfgampo cfgcpin 0.01 f 22 f 1 k w 36 m pd78p4916 three-value divider (t a = 25 ?c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input impedance z ipfg 20 50 100 k w comparator high voltage v pfgh v ref +0.5 v ref +0.7 v ref +0.9 v comparator low voltage v pfgl v ref C1.4 v ref C1.2 v ref C1.0 v csync comparator (ac coupling) (t a = 25 ?c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input impedance z icsyn 20 50 100 k w comparator high voltage v csynh v ref +0.07 v ref +0.10 v ref +0.13 v comparator low voltage v csynl v ref C0.13 v ref C0.10 v ref C0.07 v reel fg comparator (ac coupling) (t a = 25 ?c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input impedance z irlfg 20 50 100 k w comparator high voltage v rlfgh v ref +0.02 v ref +0.05 v ref +0.08 v comparator low voltage v rlfgl v ref C0.08 v ref C0.05 v ref C0.02 v recctl driver (t a = 25 ?c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit recctl+, C high level output voltage v ohrec i oh = C4 ma v dd C0.8 v recctl+, C low level output voltage v olrec i ol = 4 ma 0.8 v ctldly on-chip resistor r ctl 40 70 140 k w ctldly charge current i ohctl on-chip resistor disabled C3 ma ctldly discharge current i olctl C3 ma m pd78p4916 37 timing waveform ac timing test point serial transfer timing (sion: n = 1, 2) 0.8 v dd or 2.2 v 0.8 v test points 0.8 v dd or 2.2 v 0.8 v sckn sin son t cysk t dssk t sssk t hssk input data output data t wskl t wskh 38 m pd78p4916 serial transfer timing (only sio2) no busy processing continue busy processing terminate busy processing caution do not use busy control and strobe control whenever the external clock is selected as a serial clock. sck2 busy strb t wskl t wskh 78 t cysk t dstrb t wstrb 9101 invalid busy at active-high 2 sck2 busy strb t wskl t wskh 78 t cysk t dstrb t wstrb 9 10 10+n at active-high t sbusy t hbusy sck2 busy t wskl t wskh 78 t cysk 9 11+n at active-high 1 t lbusy t hbusy 10+n m pd78p4916 39 super timer unit input timing interrupt input timing reset input timing t wcth t wctl 0.8 v 0.8 v dd at dfgin, cfgin, dpgin, reel0in and reel1in logic level input t wcr1h t wcr1l 0.8 v 0.8 v dd at csyncin logic level input t wrsl 0.8 v reset t wnih t wnil 0.8 v 0.8 v dd nmi t wiph0 t wipl0 0.8 v 0.8 v dd intp0, intp3 t wiph1 t wipl1 0.8 v 0.8 v dd intp1, key0 - key4 t wiph2 t wipl2 0.8 v 0.8 v dd intp2 40 m pd78p4916 clock output timing t clh 0.8 v dd 0.8 v clo t clr t clf t cll t cycl m pd78p4916 41 dc programming characteristics (t a = +25 5 ?c, v ss = av ss = 0 v) parameter symbol symbol note 1 conditions min. typ. max. unit input voltage, high v ih v ih 2.4 v ddp +0.3 v input voltage, low v il v il C0.3 0.8 v input leakage current i lip i li 0 v i v ddp note 2 10 m a output voltage, high v oh1 v oh1 i oh = C400 m a 2.4 v v oh2 v oh2 i oh = C100 m av ddp C0.7 v output voltage, low v ol v ol i ol = 2.1 ma 0.45 v output leakage current i lo 0 v o v ddp , oe = v ih 10 m a v dd supply voltage v ddp v dd program memory write 6.25 6.5 6.75 v mode program memory read 4.50 5.0 5.50 v mode v pp supply voltage v pp v pp program memory write 12.2 12.5 12.8 v mode program memory read v pp = v ddp v mode v dd supply current i dd i dd program memory write 50 ma mode program memory read 30 ma mode v pp supply current i pp i pp program memory write 50 ma mode program memory read 1 100 m a mode notes 1. corresponding symbols of the m pd27c1001a. 2. v ddp is a v dd pin during programming. 42 m pd78p4916 ac programming characteristics (t a = +25 5 ?c, v ss = av ss = 0 v) prom write operation mode (page programming mode) parameter symbol note 1 conditions min. typ. max. unit address setup time t as 2 m s ce set time t ces 2 m s input data setup time t ds 2 m s address hold time t ah 2 m s t ahl 2 m s t ahv 0 m s input data hold time t dh 2 m s output data hold time t df 0 230 ns v pp setup time t vps 2 m s v ddp setup time t vds note 2 2 m s initial programming pulse width t pw 0.095 0.1 0.105 ms oe set time t oes 2 m s oe ? valid data delay time t oe 1 m s oe pulse width during data latch t lw 1 m s pgm set-up time t pgms 2 m s ce hold time t ceh 2 m s oe hold time t oeh 2 m s notes 1. correspond to symbols of the m pd27c1001a (except t vds ). 2. t vds corresponds to t vcs of the m pd27c1001a. m pd78p4916 43 prom write mode (byte programming mode) parameter symbol note 1 conditions min. typ. max. unit address setup time t as 2 m s ce set time t ces 2 m s input data setup time t ds 2 m s address hold time t ah 2 m s input data hold time t dh 2 m s output data hold time t df 0 130 ns v pp setup time t vps 2 m s v ddp setup time t vds note 2 2 m s initial programming pulse width t pw 0.095 0.1 0.105 ms oe set time t oes 2 m s oe ? valid data delay time t oe 150 ns notes 1. correspond to symbols of the m pd27c1001a (except t vds ). 2. t vds corresponds to t vcs of the m pd27c1001a. prom read mode parameter symbol note 1 conditions min. typ. max. unit address ? data output time t acc ce = oe = v il 200 ns ce ? data output time t ce oe = v il 200 ns oe ? data output time t oe ce = v il 75 ns data hold time (from oe - , ce - ) note 2 t df ce = v il or oe = v il 060ns data hold time ( from address) t oh ce = oe = v il 0ns notes 1. correspond to symbols of the m pd27c1001a. 2. t df is a time after either oe or ce rose to v ih first. 44 m pd78p4916 prom write mode timing (page programming mode) a2 - a16 a0, a1 d0 - d7 v pp v ddp v pp v ddp v ddp +1.5 v ddp v ih v il v ih v il v ih v il ce pgm oe t as t ahl t ahv hi-z t dh hi-z t ds t dh hi-z t vps t pgms t oe t ah t oeh t ceh t pw t lw t oes t vds page data latch page programming program verify data input data output t ces m pd78p4916 45 prom write mode timing (byte programming mode) cautions1. apply voltage to v ddp before applying voltage to v pp , and cut off v ddp voltage after v pp voltage is cut off. 2. the voltage, including overshoot, applied to v pp pin must be kept less than +13.5 v. 3. if a device is inserted or removed while +12.5 v is applied to v pp pin, it may be adversely affected in reliability. prom read mode timing notes 1. if data need to be read within t acc , the maximum delay time of oe active level input from ce falling should be t acc C t oe . 2. t df is the time after either oe or ce first rose to v ih . programming program verify hi-z data input data output hi-z hi-z d0 - d7 a0 - a16 v pp v pp v ddp v dd +1.5 v ddp v ddp v ih ce v il v ih v il v ih v il pgm oe t ces t pw t vds t vps t ds t as t dh t ah t df t oe t oes valid address hi-z data output hi-z d0 - d7 a0 - a16 oe ce t ce t df note 2 t oe note 1 t oh t acc note 1 46 m pd78p4916 6. package drawing j n m p 80 81 50 100 pin plastic qfp (14 20) 100 1 31 30 51 g detail of lead end s 5 5 c d a b h q k l f m i p100gf-65-3ba1-2 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 0.6 0.30 0.10 0.15 20.0 0.2 0.929 0.016 0.031 0.024 0.006 0.026 (t.p.) 0.795 note m n 0.10 0.15 1.8 0.2 0.65 (t.p.) 0.006 0.031 +0.009 ?.008 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.012 0.551 0.8 0.2 0.071 p 2.7 0.106 0.693 0.016 17.6 0.4 0.8 +0.008 ?.009 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.004 ?.003 0.004 m pd78p4916 47 7. recommended soldering conditions this device should be soldered and mounted under the following conditions. for details about the recommended conditions, refer to the document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 7-1. surface mounting type soldering conditions m pd78p4916gf-3ba: 100-pin plastic qfp (14 x 20 mm) soldering method soldering conditions symbol infrared rays reflow peak package's surface temperature: 235 ?c, reflow time: 30 seconds or less ir35-00-2 (at 210 ?c or higher), number of reflow processes: 2 or less 48 m pd78p4916 appendix a. development tools the following development tools are prepared for system development using the m pd78p4916. language software ra78k4 note 1 assembler package common to the 78k/iv series cc78k4 note 1 c compiler package common to the 78k/iv series cc78k4-l note 1 c compiler library source file common to the 78k/iv series prom writing tool pg-1500 prom programmer pa-78p4916gf programmer adapter connected to the pg-1500 pg-1500 controller note 2 control program for pg-1500 debugging tool ie-784000-r in-circuit emulator common to the 78k/iv series ie-784000-r-bk break board common to the 78k/iv series ie-784000-r-em emulation board common to the 78k/iv series ie-784915-r-em1 emulation board for evaluation of the m pd784915 subseries ie-78000-r-sv3 interface adapter when using ews as a host machine ie-70000-98-if-b interface adapter when using pc-9800 series (except notebook type) as a host machine ie-70000-98n-if interface adapter and cable when using notebook type pc-9800 series as a host machine ie-70000-pc-if-b interface adapter when using ibm pc/at tm as a host machine ep-784915gf-r emulation probe common to the m pd784915 subseries ev-9200gf-100 conversion socket for 100-pin plastic qfp to mount a device on a target system sm78k4 note 3 system emulator for all 78k/iv series devices id78k4 note 3 integrated debugger for ie-784000-r df784915 note 4 device file common to the m pd784915 subseries real-time os rx78k/iv note 4 real-time os common to the 78k/iv series mx78k4 note 2 os common to the 78k/iv series * * m pd78p4916 49 notes 1. ? pc-9800 series (for ms-dos tm ) based ? ibm pc/at and compatibles (for pc dos tm , windows tm , ms-dos, and ibm dos tm ) based ? hp9000 series 700 tm (for hp-ux tm ) based ? sparcstation tm (for sunos tm ) based ? news tm (news-os tm ) based 2. ? pc-9800 series (for ms-dos) based ? ibm pc/at and its compatibles (for pc dos, windows, ms-dos, and ibm dos) based 3. ? pc-9800 series (for windows on ms-dos) based ? ibm pc/at and its compatibles (for pc dos, windows, ms-dos, and ibm dos) based ? hp9000 series 700 (for hp-ux) based ? sparcstation (for sunos) based 4. ? pc-9800 series (for ms-dos) based ? ibm pc/at and compatibles (for pc dos, windows, ms-dos, and ibm dos) based ? hp9000 series 700 (for hp-ux) based ? sparcstation (for sunos) based remark the ra78k4, cc78k4, sm78k4, and id78k4 should be used in combination with the df784915. * 50 m pd78p4916 ev-9200gf-100 a d e b f 1 no.1 pin index m n o l k s r q i h g p c j ev-9200gf-100-g0 item millimeters inches a b c d e f g h i j k l m n o p q r s 24.6 21 15 18.6 4-c 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.969 0.827 0.591 0.732 4-c 0.079 0.031 0.472 0.89 0.996 0.236 0.654 076 0.323 0.315 0.098 0.079 0.014 0.091 0.059 f f f f appendix b. socket drawing and recommended footprint figure b-1. ev-9200gf-100 drawing (for reference purpose only) * m pd78p4916 51 figure b-2. recommended ev-9200gf-100 footprint (for reference purpose only) f h e d a b c i j k l 0.026 1.142=0.742 0.026 0.748=0.486 ev-9200gf-100-p1 item millimeters inches a b c d e f g h i j k l 26.3 21.6 15.6 20.3 12 0.05 6 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 1.035 0.85 0.614 0.799 0.472 0.236 0.014 0.093 0.091 0.062 0.65 0.02 29=18.85 0.05 0.65 0.02 19=12.35 0.05 f +0.001 ?.002 +0.002 ?.002 +0.001 ?.002 +0.003 ?.002 +0.003 ?.002 +0.003 ?.002 +0.001 ?.001 +0.001 ?.002 f +0.001 ?.002 f f g f f dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution 52 m pd78p4916 appendix c. related documents document related to device title document no. japanese english m pd784915 subseries users manual C hardware u10444j u10444e m pd784915 subseries special function register table u10976j 78k/iv series users manual C instructions u10905j u10905e 78k/iv series instruction table u10594j 78k/iv series instruction set u10595j 78k/iv series application note C software basics u10095j development tool documents (users manual) title document no. japanese english ra78k series assembler package language eeu-809 eeu-1399 operation eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 cc78k series c compiler language eeu-656 eeu-1280 operation eeu-655 eeu-1284 cc78k series library source file eeu-777 pg-1500 prom programmer eeu-651 eeu-1335 pg-1500 controller pc-9800 series C ms-dos base eeu-704 eeu-1291 pg-1500 controller ibm pc series C pc dos base eeu-5008 u10540e ie-784000-r eeu-5004 eeu-1534 ie-784915-r-em1 ep-784915gf-r u10931j id78k4 integrated debugger C reference u10440j ieu-1412 embedded-software documents (users manual) title document no. japanese english rx78k/iv series real-time os basics u10604j installation u10603j debugger u10364j caution the contents of the documents listed above are subject to change without prior notice to users. be sure to use the latest edition when starting design. * m pd78p4916 53 other documents title document no. japanese english semiconductor device package manual iei-635 iei-1213 semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices iei-620 iei-1209 nec semiconductor device reliability/quality control system iem-5068 electrostatic discharge (esd) test mem-539 guide to quality assurance for semiconductor devices mei-603 mei-1202 microcontroller-related product guide - third party products mei-604 caution the contents of the documents listed above are subject to change without prior notice to users. be sure to use the latest edition when starting design. * 54 m pd78p4916 [memo] m pd78p4916 55 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. m pd78p4916 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94.11 the application circuits and their parameters are for reference only and are not intended for use in actual design-in's. fip is a trademark of nec corporation. ms-dos and windows are trademarks of microsoft corporation. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. |
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